corsair
Control and Status Register map generator for HDL projects
Possibly Available
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Evidence-backed skills
Repositories
proto245
🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
axi_vip_demo
Xilinx AXI VIP example of use
usb20dev
USB 2.0 FS Device controller IP core written in SystemVerilog
openocd-svd
Standalone OpenOCD and CMSIS-SVD based peripheral register viewer written on Python
adc-eval
📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC
svjson
🇯 JSON encoder and decoder in pure SystemVerilog
pyhdlsim
Example of Python and PyTest powered workflow for a HDL simulation
vfd-ps
Power supply and filament driver for vacuum fluorescent display (VFD)
pip-hdl
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
kicad-archive-project
Python script to archive KiCAD project
nixie-ps
High voltage power supply for nixie tubes