Developer profile

Yin Weijie

@yinweijie on GitHub ↗

Possibly Available

Repositories

MFiX_lab

Some MFiX code tests

Fortran★ 5⑂ 3

cmn700_min_repro

Minimal Verilator bug repro: combinational always @* with for-loop writing variable bit-selects of a packed struct member is scheduled into eval_initial (runs once) -> stale value, back-to-back flit overwrite

SystemVerilog★ 0⑂ 0

mit-study-group

MIT体系结构公开课学习社区作业记录

C★ 0⑂ 0